SPI input delay number configuration
| DIN0_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |
| DIN1_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |
| DIN2_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |
| DIN3_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |
| DIN4_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |
| DIN5_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |
| DIN6_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |
| DIN7_NUM | the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,… Can be configured in CONF state. |